In the manufacture of semiconductor products, substrates (e.g., semiconductor wafers) are processed by successively depositing, etching, and polishing various layers to create semiconductor devices. More specifically, plasma-enhanced etching and wafer bonding have often been employed in these processing steps.
However, etching processes tend to eat away at the substrate edge or bevel, and wafer bonding processes tend to create negative slopes at the wafers' edge or bevel while exposing bonding materials. FIGS. 1A-B and 2A-B show examples of these problems in via etching and in wafer bonding.
FIGS. 1A and 1B demonstrate the problem of etching processes eating away at the substrate edge or bevel in a via etch process. FIG. 1A shows a substrate 100 and a substrate edge region 102 prior to etching. In FIG. 1A, mask 106 remains on substrate 100 after etching. Thickness 110 reflects the original thickness of the substrate prior to etching.
FIG. 1B shows a substrate edge region 112 after etching. In FIG. 1B, area 114 represents the area where the substrate edge or bevel turns into black silicon post-etch. Black silicon is a rough part of the original substrate that has been eaten away by the etchant. Thickness 120 of FIG. 1B is substantially less than the original thickness of the wafer, substantially increasing the likelihood of bevel collapse. Furthermore, the black silicon area 114 can trap contamination that may pollute the processing steps in the future.
To address the bevel collapse problem described above in etching or other type of material removal or punch-through processes, thick protective films or anti-etching sacrificial films at the substrate edge or bevel are used to minimize substrate bevel collapse. Another approach of wafer bevel protection utilizes a process kit known as a shadow ring, which is placed on top of bevel area of the wafer or slightly above the wafer. However, the shadow ring oftentimes introduces tilting and particle issues. Accordingly, this process requires many stages to define the film at the substrate edge. This is problematic especially if the film deposition at the substrate edge or bevel requires separate special equipments.
FIGS. 2A-B illustrate an example of the problem in wafer bonding near the edge or bevel. FIG. 2A shows lower wafer 202, upper wafer 204, and bonding material 206. The bonding material is typically some type of organic material. In general, a Chemical Mechanical Polish (CMP) is performed after the wafer bonding process. FIG. 2B shows the post-CMP bonded wafers. Specifically, region 220 shows that the bonding material is exposed at the edge or bevel of the wafers. Having exposed bonding material can create side defects and other unpredictable effects. Furthermore, region 220 shows a negative slope near the edge or bevel of the wafers. For a variety of reasons, semiconductor manufacturers may prefer positive slope geometries near the edge of a wafer. The negative slope and the exposed bonding material may present other problems such as undercut issues or delamination issues.
To address the bevel edge negative slope problem, CMP may be employed to shape the edge or bevel back to a positive slope. However, this solution is costly, and does not solve the problem of the exposed bonding material.